To see the structure hidden in this diagram we have to look at it through algebra and programs.

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There is nothing wrong with the approach described but I fail to see that there is anything novel here either. Circuits have been modeled as state machines since the 60s (e.g. Booth 67), there is a wealth of literature on the correspondence between state machines, automata and strings, and so forth. All of this has been done before, and more completely.

I am sure that one could look in most computer science curricula and find almost all of this material being taught at the undergraduate level.

I’m really embarrassed for the entire profession here. Of course circuits have been modeled as state machines – well before 1967 in fact. Booth’s 1967 book is one of innumerable surveys.  The paper showed an alternative way of representing state machines and illustrated their use on the time sensitive behavior of combinational circuits where they are not usually employed because the number of states is so great as to overwhelm standard methods.  The specific methods used in this papers, as far as I know, are not used elsewhere in the literature – and I still don’t know any different because the CAV2010 reviewer was unable to provide a reference. To me, this is a mark of humbug. Look, if you are going to tell some poor author that their work is retelling some well known tale, you should at the very least be able to point to the well known explications. Creditably enough, CAV2010 offers a rebuttal period for reviews: but even given a second chance, and an explicit request for a reference, both the author of the review and the program committee failed.  An assertion is made that the material is covered in “most computer science curricula” and when challenged, the assertion is just left as is. No wonder so much of academic computer science is mired in stale repetition of old material when basic standards of scientific rigor are discarded by the people who are supposed to be enforcing the rules.

I don’t want to seem entirely ungrateful for the work of the reviewers: one of whom gave a perfectly rational and solid reason for rejecting the paper.

Conclusion: an elegant paper, but doomed for CAV by lack of any attempt at automation or convincing evidence that automation of the methods described would be a scientific advance.

I can’t really argue with that. The paper does not either describe automation or attempt to make an argument of why automation would succeed – although I am in no doubt about the second question. Perhaps the paper is not suitable by reason of the focus of the conference. But of 4 reviews, this reviewer was the only one who appeared to understand the material. One of the other reviewers actually responded to the rebuttal with this:

About the KR theorem and feedback, an ordinary finite state automaton “encodes” implicitly the feedback information of the underlying sequential circuit in its states, so I would be surprised that the theorem is not applicable to digital circuits with feedback

Ok. The KR (Krohn-Rhodes) theory is based on a decomposition called “loop free”. Let me type that again LOOP FREE.  The theory is concerned with the decomposition of state machines into pipelines where components can be ordered so that the output of component i depends only on the input to the system and the outputs of components j<i . What I show in the paper is how to describe one of the simplest and most beautiful achievements of Computer Engineering, a SR-latch via the interconnection of state machines that represent logic gates. The SR-latch is constructed with cross-coupled gates where the output of each gate feeds back into the input of the other gate. When the output of gate G1 feeds into the input of gate G2 and the output of G2 feeds into the input of G1, we have what is known in the technical literature as a “loop”. While the reviewer would not be surprised if a loop-free product could be used to describe a loop,  the comment makes me doubt his/her grasp on the basics of the material (BTW: the identity of this reviewer is known to me, but I’ll leave to him/her to respond or not).

One of the other reviewers included (among others) two comments  that I noted were wrong, but were not modified or defended.

2. The term “propagation delay”: It seems that you blend different concepts into this single term, namely the duration that an input has to be held stable in order to be sure that it will be reflected by the output and the latency of a circuit in forwarding such a sufficiently stable input to its outputs. While your model, by lumping together the two into a single latency, is a conservative approximation of more detailed models, you may want to make sure that your terminology is in accordance with accepted terminology. it.

Here the reviewer apparently does not understand the difference between latch time and propagation delay. Have those definitions changed since I last looked at a digital circuits book? “The propagation delay t_p of a signal path is the amount of time that is takes for a change in the input signal to produce a change in the output signal” (Wakerly, 1990, P 76).

3. The abstraction of your latch leaves the case (set,reset): (0,0) -> (1,1) unspecified, which is fine. You may, however, want to mention this detail in the accompanying text.

Ah well, the second week of Digital Electronics II is not for everyone. “However if we negate both inputs simultaneously, the latch goes into an unpredictable next state and it may in fact oscillate or enter the metastable state.” (Wakerly 1990 P355). See it’s really not so hard to provide a citation.

There’s actually a lot more to ridicule in these reviews – I’ll post more on request, but I do want to look at one more comment from Reviewer4.

I still believe that this paper lacks motivation and new results for being accepted. As the author says himself, the paper is about a technique for specifying automata, and I am not convinced why not doing it directly with automata, using standard and well-studied techniques. For instance, given that the propagation delays of the gates are modeled using discrete time, why embedding them directly into the definition of gates (even underspecified), instead of modelling them directly with I/O finite state machines (or sequential circuits with feedback)?

It’s not at all clear to me what  modeling a gate as a sequential circuit with feedback even means. In terms of digital circuit engineering, a gate is a combinational circuit, not a sequential circuit. The cool thing about a cross-coupled latch is that the feedback produces sequential properties from combinational circuits. So this comment is quite obscure. On the other hand, I/O automata (from Lynch/Tuttle) are a good example of the augmented automata that I’m deliberately avoiding because of their mathematical ugliness. You can take classical state machines and add all sorts of stuff to them: clocks, fairness conditions, oracles depending on the Axiom of Choice, steroids, flavor enhancers, and so on.  The “standard and well-studied techniques” Reviewer4 has in mind are almost certainly timed and hybrid automata which are types of augmented automata. But the argument made in my paper is that the austere flavor of classical automata theory is strong enough to model timing without additives. Rather than responding to this argument, the Reviewer asks why I don’t use the “standard” methods with additives.

It’s certainly possible that the work described in the paper lacks interest to anyone but me ( the “crank” hypothesis). But lacking credible reviews, it’s hard to make any conclusion at all.

A response.

Hi Victor, good to hear from you.

About your CAV paper, don’t get pathetic. Each PC member has to review in a short time numerous papers and he cannot afford the time needed to give full feedback to the author of a paper which shows strict disconnectedness with contemporary verification. Instead of thanking (or even apologizing) to the PC members for the fact that they bothered to read your paper and give you some feedback (one minute browsing was sufficient to predict its rejection) you still complain and make useless noise.

I will send you my rejected paper and its reviews, if you enjoy reading such things.

Pathetic! Ouch.

In other matters

For a variety of reasons, this reminds me of  a conference I attended in Salvador Brazil many years ago which was like something out of a Magical Realism novel involving lachrymose Argentines who longed to teach meringue, drum bands, unbearably tedious talks, dreamlike missed airplane sequences,  a moment when I was sure that Amir Pnueli, his wife, and myself were about to be assaulted while we were discussing the Israeli novel Blue Mountain which according to Pnueli, was set in his home town, random appearances of gigantic fashion models, an abandoned building in which rooster fighting was taking place,  the most delicious beer ever drunk in world history, a peculiar lecture on Fra Angelico and the relationship between New Mexico and Hassidism (“you must look at the white spaces between the words”) , a hero named Hercules, and much more. I returned from the trip to a faculty meeting chaired by Jean Louis Lassez.  Did any of it even really happen? The conference also provided me with an astounding article review: the reviewer explained that I had made an elementary error when I proved something about a set without taking into account the ordering of the set. Even the Baal Shem Tov would not be able to discern meaning in such a comment.

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If you visualize the graph of Q, you can see it contains non-trivial loops – which means that the monoid associated with Q contains groups. The advantage of decomposing Q into a product of smaller machines is that this might guide a smarter implementation. Well, I’m kind of cheating here, because programmers have found a variety of smart implementations that do strip out the group structure.

The easy decomposition produces two counters, and a collection of k storage elements that are loop free state machines: an input “store x” moves the machine to a “x” state. They do contain loops but only trivial ones. The counters are group machines. We number the storage cells 0 to k-1.  We can have one mod k counter that “points” to the tail of the queue and one that counts the size of the queue. On an enq operation the enqueued value is stored in the storage element identified by subtracting the size from the tail mod k,   and the size is increment mod k+1. An enq operation when the size=k is ignored and has no effect. On a deq, the size is decremented and the tail is incremented by one mod k+1. What we’ve done is construct a system in which the state machine monoids are two cyclic groups and k-aperiodic monoids. If we then switch to more complicated data structures, like ordered lists, it’s not that hard to see how a permutation group might be used to manipulate pointers to a pile of storage locations. For example (n1,n2,n3,n4,blank, n5,n6) might be an ordered list with n5 and n6 being free. An enqueue would generate some shuffle to say, (n1,n2,n5,n3,n4,blank,n6) and then a dequeue would produce (n2,n5,n3,n4,blank, n6,n1).

A nice property of groups is that “undo” always works. So if the data in the storage elements can be marked in some way, a deq or enq can be undone by subtracting mod k or permuting backwards.

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In digital logic, a “combinational” circuit like a logic gate has can be associated with a time T so that the output depends only on input signals applied over the last T time units. If the propagation delay is T, then signals applied T+n time units ago are irrelevant to current state.  For example, an AND gate with propagation delay T has output 1 if all inputs have been set HIGH over the last T time units. For a sequential circuit, like a latch, there is no magic time T. Suppose we set the stored value in the  latch at time T1 and then signal it to hold the value. No matter how long the latch is held, we have to go back to absolute time T1 to find out what is in the latch. It’s worth noting however, that it’s often very useful to make a sequential circuit have a reset mode where it behaves like a combinatorial circuit. That is, we want to be able to say: no matter what previous signals have done to a memory device, some sequence of signals will clear it and, for example,  put the number 3 in it. More on this below.

Take a Moore machine M and write State(M,w) for the state reached by following input string “w” from the initial state. I’m limiting us to complete Moore machines where State(M,w) must be defined for every w.  Say M is combinational if there is some T so that if w=uz and length(z)>T then State(M,w)= State(M,z) . So the idea is that there is a T so that the last T inputs determine state for M. Call T the “depth” of M. As an example, suppose M represents a memory location and the inputs are just data values to store. Then we only need the last input, T=1.  If M is an AND gate with two pins and a delay of 2, then we can think of inputs as numbers 0,1,2,3 representing their 2 bit encodings: 0 for 00, 1 for 01, 2 for 10 and 3 for 11.  States can be pairs [x1,x2] representing the last two inputs so that if the state is [a,b] and input “c” is received, the new state is [c,b].  The state is actually a shift register. Suppose that the states are all pairs [x1,x2] where x1 and x2 are in the set {-1,0,1,2,3} with “-1″ representing  an unknown signal. Then [3,3]  has output 1, [x1,x2] where both x1 and x2 are greater than -1 and less than 3 outputs 0 and the others have undefined output. The initial state is [-1,-1]. Obviously this machine is combinational with depth T=2. The intuition here is that combinatorial state machines will always “swim” to a fixed state given a fixed sequence of inputs of sufficient length. Obviously, this is a useful property of a device and even for sequential devices we are going to want some single or sequence of “reset” operations that, no matter what the current state, will force a reset to a known state. That is, for our latch, we’d want to force it to an assigned latched value, no matter what, if anything, it had previously latched. So properly designed sequential circuits are going to look like some combination of combinatorial and sequential circuit.

Now consider products of state machines. The method I’ve been using for representing state machines as maps f:InputSequences ->Outputs is convenient for products. If f represents a state machine M, then f(w) = Output(State(M,w)). If f represents a combinational state machine of depth T then f(wuz)= f(uz) whenever length(u)>T because State(M,wu)=State(M,u) so State(M,wuz)=State(M,uz) so the outputs must be the same.  Say F(w) = (g1(w1) …, gn(wn)) is a product under connection function Phi and map w |-> w1 … ,wn if when w=empty then wi = empty for all i and if when w maps to wi then wa maps to wi.Phi(a,i,F(w)) with ‘.’ representing string concatenation. Say that F is a cascade product if and only if  Phi(a,i,(x1 … xn)) depends only on xj for j < i. That is, in a cascade product, information only flows from lower numbered factors to higher numbered ones: there is no feedback in a cascade product. If g1 …,gn are combinatorial AND Phi(a,i,(x1 …,xn)) !=empty for any combination of parameters, and F is a cascade product, then F must be combinatorial. For proof, suppose Ti is the depth of each component gi and suppose w=uv where length(v)> T1. Then w1= u1.v1 where length(v1)> T1 so g1(v1)=g1(w1) and more than that g1(w1.z)=g1(v1.z) for all z.  That means Phi(a,i,F(wa))=Phi(a,F(va)) by the cascade property. And so on – eventually we see that the depth of F is the sum of the depths of the factors! For intuition, first we need enough inputs to steer factor 1 to a known state, then factor 2 and so on.

Given a state machine M with states S, we can associate a map from S to S with every string of inputs w so that F(M,w)(s)=s’ if and only if w leads from s to s’. This set of maps forms a monoid under ordinary function compositions  and since F(M,w)(F(z)(s))= F(M,wz)(s) then F(M,w)+F(M,z)= F(M,wz) where + is the monoid operation and not anything necessarily related to arithmetic. The empty string produces the monoid identity F(M,empty)(s)=s.  Look at the monoid structure of combinatorial state machines and note that unless the monoid is trivial, then  F(M,w)=F(M,empty) only if w=empty – there are no other identities.

The proof is easy. Suppose M is combinatorial  with depth T, the monoid is not trivial so that for some v we have F(M,v) != F(M,empty)and suppose F(M,z)=F(M,empty).  Then if z is not empty let Z consist of a string of concatenated z’s that is longer than T  so Z=zzzzzz …. stretched out to a length greater than T. By the combinatorial property, for any u, F(M,uZ)(s)=F(M,Z)(s) but because F(M,z)=F(M,empty) we also know F(M,uZ)(s)=s so F(M,w)(s)=s for all w and s which implies the monoid is trivial after all. It’s also worth pointing out that the combinatorial monoids seem to be a proper subset of the aperiodic monoids ( http://www.liafa.jussieu.fr/~jep/PDF/HandBook.pdf ). Consider the state machine with states {0,1,2} and inputs {a,b} so that, treating the inputs at maps from state to state, a(0)=1 and b(0)=2 for any non-zero state we have x(s)=s. The monoid is clearly aperiodic since a²=a ³ , a²(0)=1 and a²(s!=0)=s. But the state machine is not combinatorial.

Well, more later, but that’s what I have semi-clearly explicated for now. I’ll leave you with this photograph of Camille Jordan who lived in an unenlightened era that did not make clear demarcations between mathematics and mere engineering.

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Well, it seems our friends at Sun have decided that their Spice^tm Enhanced brains are completely sufficient to create an entirely new – but far simpler, mind you – module system for the JDK.  Mark “I’m just a simple Guild Navigator” Reinhold has spent a number of blog posts doing the electronic equivalent of the Dance of the Seven Veils, culminating with revealing the aptly named Project Jigsaw. (from “Hal”).

Ok, so a barely disguised (“Emerald City” plus “House Harkonnen” – what part of XXXwood City could that be in ?)  snarky insider post on an absolutely classical dumb Sun move is now topical enough to reference. And it combines utter snarkiness with completely geeky references to a horrible sci-fi book and it is written by someone who calls himself “Hal”. Perfecto!

This reminds me of how years ago “L” who once worked for Sun calls up friends in the file system group to explain that tests are showing Solaris file system operation 4 or 5 times slower than Linux. Responses range from incredulity to boredom, but do not include anything as humble as “we can download and test”. Because customers are going to be so grateful for the brilliance of the core group, that minor crap like performance won’t make any difference.

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rcvm(fd, &buf, n, func); // call “func” when the data arrives – pass it the return val and arguments to read as well

then

while(1){

rcvm(fd,&ptr++,n,got);

if(noresources)wait();

}

got(fd,&p,n,code){

look at message

queue_response

return;

}

Worse or better?

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[0018]For incoming network packets, the following is done during the logging mode. When a packet is received, an event-request is posted for the VMM, at Block 210. When the VMM processes the event, it stops the VM, synchronizes the guest VCPU state, and then calls into the device emulator (i.e., device emulation software event handler), at Block 220. The device emulator logs an event at Block 230. Then, the device emulator receives the packets, and logs their contents, at Block 240. The last packet logged is marked so that during replay the device emulator can know when the last packet for this event occurs in the log.

[0019]During replay the following occurs: When an I/O event is encountered in the log, the device emulator (i.e., device emulation software event handler) is called by the VMM. The device emulator reads all packets that were logged, and copies them into the memory of the VM. In this way, the receive queue of packets is updated at the exact same point in the instruction execution sequence during logging and replay.

VMWARE application.

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A parallel computer system which has a primary task processor, a second primary task processor, a secondary task processor acting as a backup for the second primary task processor transfers messages by: sending messages from the primary task processor to the second primary processor with the second primary task processor operating on the messages by initially storing a received message in a queue and thereafter reading the message from the queue for processing in accordance with the task associated therewith and accumulating a count of the messages read from its queue; and sending the same messages from the first primary task processor to the secondary task processor which stores the messages in a message queue for possible use if the second primary task processor fails. If a primary task processor fails after processing a given number of messages, the secondary task processor associated therewith starts processing the messages in its queue but after having discarded the first given number of messages.

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