We added the “reservation” capability to RTCore real-time POSIX threads a couple of years ago. Normally, the client platform operating system shares the processor with RTCore threads as a completely pre-emptible low priority thread. This works exceptionally well. Worst case interrupt latencies of under 10 microseconds on Opterons and under 20 on Arm9s are possible – and this is worst case under load and measured over days or weeks not the usual lipstick-on-pig numbers common in the industry. For timer driven threads, we can make these times better by wasting a little compute time using the timer advance feature of RTCore, but for true “every microsecond matters” pedal-to-the-metal hard real-time, processor reservation is the way to go and the widespread availability of multi-core processors makes the case more compelling. Reservation works by making a processor core disappear from the view of the symmetric multiprocessing (SMP) client operating system so that only real-time threads run there. Reservation on RTCore is a mature technology that has been in use production systems for years. Interrupts are redirected, cores can be reserved and unreserved dynamically, reservation works for user-space memory protected real-time threads and each real-time core runs its own cleanly separated real-time scheduler. The performance improvements are dramatic on true multiprocessors and nearly as dramatic on multi-core. With multi-core processors, we can start treating processor cores as allocatable resources. Consider a 2 core system where Windows XP runs under a virtual machine and real-time threads reserve the second core – executing out of L2 cache. The screen-shot in this note shows XP running while a real-time thread runs the “jitter” test on the second processor. Because processor reservation is designed within the POSIX API and on the basis of the “decoupled real-time” paradigm at the heart of RTCore, it offers the same interface for SMP and multi-core and has scaled up to multi-core along with the client operating systems.